A speech CODEC scheme which is realized by a one-chip digital signal processor (DSP) has been proposed by Nakamura and Hioki, achieving a compact, lightweight CODEC device suitable for use in equipment such as digital portable telephones. (See Japanese Patent Application Laid-open No. Hei 6-77910).
In the proposed speech CODEC scheme, a coding and decoding process for each frame is comprised of a frame process and a plurality of subprocesses. Under such conditions that coded data is received and transmitted in units of a frame at a predetermined timing, the sequence of the coding and decoding subprocesses is determined in advance to minimize coding delay time and decoding delay time, where the coding delay time is the time difference between an input time of speech data to be coded and an output time of coded data, and the decoding delay time is the time difference between an input time of coded data to be decoded and an output time of decoded data.
In the one-chip DSP CODEC device, this CODEC scheme can reduce the time interval from transmission to reception of coded data to an allowable time interval. More specifically, the time interval from a transmission time point of coded data as obtained by the coding process to a reception time point of coded data to be decoded by the decoding process can be reduced to the allowable time interval prescribed in mobile communications standards (e.g. 5.75 msec in GSM).
However, when a data signal of changing the transmission timing is received for each frame, the transmission timing of coded data is varied, usually delayed. When receiving the transmission timing charge data, a conventional speech CODEC system operates as shown in FIG. 1.
FIG. 1 shows the main process of a conventional speech CODEC system, in which the coding and decoding process is comprised of four coding subprocesses, four decoding subprocesses, and a waiting subprocess where neither coding nor decoding is made during the remaining time in a frame.
Referring to FIG. 1, it is checked whether the timing data indicating the transmission timing of coded data has been received (step 11). If affirmative, it is then checked whether the transmission timing has been adjusted for the frame (step 12). If negative, it is then checked whether the timing data includes the data of changing the transmission timing (step 13). If the timing change data exists, transmission timing is adjusted (step 14). The subprocess to be executed next is then selected based on the predetermined sequence (step 15), and the selected subprocess is executed (step 16).
However, in the above conventional execution method, even when the transmission timing is delayed, the coding subprocesses 0-3 are executed in fixed timing regardless of the transmission timing delay. This causes the coding process to finish considerably before the actual transmission timing, which means that the coding delay time may extend up to one frame.